LiteDRAM 开源可配置 DRAM 核心解析

原标题：The DRAM interface and the PHY (why a DDR3+ interface must be tuned at boot)

38AI 研判分

LiteDRAM 是 LiteX 生态中基于 Migen 实现的小体积可配置 DRAM 控制器核心，提供厂商无关的通用 SDR PHY，支持 1:1 或 1:2 频率比，并已在 Xilinx、Altera、Lattice 平台验证。项目强调 DDR3 及以上接口需在启动阶段完成 PHY 时序调校，可作为 LiteX 库使用或生成 Verilog RTL 集成到标准设计流程。

关联知识实体

工具LiteX 术语物理层工具Migen 工具LiteDRAM

报道正文

本文目录9 个章节

文本

                                 __   _ __      ___  ___  ___   __  ___
                                / /  (_) /____ / _ \/ _ \/ _ | /  |/  /
                               / /__/ / __/ -_) // / , _/ __ |/ /|_/ /
                              /____/_/\__/\__/____/_/|_/_/ |_/_/  /_/

                                   Copyright 2015-2026 / EnjoyDigital
                               A small footprint and configurable DRAM core
                                        powered by Migen & LiteX

[> Intro

LiteDRAM provides a small footprint and configurable DRAM core.

LiteDRAM is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteDRAM can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

PHY:

Generic SDR PHY (vendor agnostic, tested on Xilinx, Altera, Lattice; 1 or 1 frequency ratio)
Xilinx Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1 or 1 frequency ratio)
Xilinx Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1 or 1 frequency ratio)
Xilinx Artix7/Kintex7/Virtex7 LPDDR4 PHY and LPDDR5 PHY (each with a Verilator simulation PHY and DRAM model)
Xilinx Artix7 RPC DRAM (Etron Reduced Pin Count) PHY (with a Verilator simulation PHY)
Xilinx Kintex/Virtex Ultrascale (Plus) DDR3/DDR4 PHY (1 frequency ratio, optional read VREF scan on Ultrascale+ DDR4)
Lattice ECP5 DDR3 PHY (1 frequency ratio, or 1 with ecp5ddrphy_with_ratio)
Lattice Nexus DDR3 PHY (1 frequency ratio)
Gowin GW2A DDR3 PHY (1 frequency ratio)
Gowin GW5A DDR3 PHY (1 or 1 frequency ratio)
DFI-level SDRAM simulation PHY/model (SDR/DDR/LPDDR/DDR2/DDR3/DDR4) for Verilator (litex_sim, litedram_gen --sim)

Core:

Fully pipelined, high performance.
Configurable commands depth on bankmachines.
Auto-Precharge.
Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).

Frontend:

Configurable crossbar (simply use crossbar.get_port() to add a new port!)
Ports arbitration transparent to the user.
Native, AXI-MM or Wishbone user interface.
DMA reader/writer.
BIST.
ECC (Error-correcting code)

[> FPGA Proven

LiteDRAM is already used in commercial and open-source designs:

HDMI2USB: http://hdmi2usb.tv/home/
NeTV2: https://www.crowdsupply.com/alphamax/netv2
USBSniffer: http://blog.lambdaconcept.com/doku.php?id=products:usb_sniffer
and others commercial designs...

[> Possible improvements

add Avalon-ST interface.
add support for Altera devices.
... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.

[> Documentation

The DRAM Controller & PHYs manual is the reference of LiteDRAM: a nightly PDF and HTML page are published on the manual-nightly release. Sources in doc/manual (build: python3 doc/manual/build.py, outputs in build/doc/):

Understand: introduction, DRAM in a nutshell, the DRAM interface and the PHY.
The core: architecture, controller, ports and frontends, initialization and calibration.
The PHYs and memories: DDR PHYs, LPDDR4, LPDDR5 and RPC (in development), memory modules.
Use it: supported FPGAs and boards, getting started, integration, examples, simulation, debugging.
Appendices: registers, build options, glossary, performance and resources.

[> Getting started

Install Python 3.6+ and FPGA vendor's development tools.
Install LiteX and the cores by following the LiteX's wiki installation guide.
You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.

[> Standalone core generation

A standalone Verilog core (controller + PHY + init firmware, with native/Wishbone/Avalon/AXI/FIFO user ports) can be generated from a YAML description:

$ litedram_gen examples/arty.yml

See doc/gen.md for the command line, the YAML keys, the native/Wishbone port protocols and the examples, and the Integration chapter of the manual.

[> Tests

Unit tests are available in ./test/. To run all the unit tests:

$ python3 -m pytest test

test_examples.py builds the LiteX BIOS (RISC-V GCC toolchain) and test_lpddr4.py/test_lpddr5.py are long simulations: the CI runs them only in its full job (with LITEDRAM_TEST_FULL=1 to enable the slow configurations); skip them with:

$ python3 -m pytest test --ignore=test/test_examples.py --ignore=test/test_lpddr4.py --ignore=test/test_lpddr5.py

Tests can also be run individually:

$ python3 -m pytest test/test_name.py

[> License

LiteDRAM is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteDRAM for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

tell us that you are using LiteDRAM
cite LiteDRAM in publications related to research it has helped
send us feedback and suggestions for improvements
send

（注：更多技术实现细节与完整 API 文档请查阅原项目 README）